A 2.4 TO 3 Gb/s REFERENCE-LESS HALF-RATE CDR WITH ADAPTIVE EQUALIZER IN WIRELINE RECEIVERS

Abstract

This paper presents a 2.4 to 3 Gb/s reference-less half-rate clock and data recovery (CDR) with combined adaptive equalizer (EQ) in wireline receiver. A wide-band receiver based on this structure is appropriate for a high-speed wireline systems. The broadband CDR achieves by using a two-step frequency tracking scheme: coarse and fine. In addition, in this work the coarse/fine frequency acquisition processes operate simultaneously to obtain a fast frequency acquisition time. The adative continuous-time linear equalizer (CTLE) based on sampled data edge counting is employed to achieve both short adaptive time and low power dissipation. A combination of EQ and CDR is proposed to achieve fast data recovery and processing times for the receiver. The proposed receiver is implemented in 180 nm CMOS process. It has the adaptive time of 4.4 µs and a frequency acquisition time of 3 µs for the tracking range from minimum frequency to maximum frequency of the voltage controlled oscillator (VCO). The receiver circuit has shown peak-to-peak jitter in recovered clock and data of 40 ps and 70 ps, respectively, with 3 Gb/s input data, whereas it consumes 42.7 mW at a 1.8-V supply.