A 0.1 TO 1.65 GHz VOLTAGE CONTROLLED OSCILLATOR (VCO) IN 180 nm CMOS PROCESS

Abstract

This paper presents design of voltage controlled oscillator (VCO) circuit applied to wide-band clock and data recovery circuits in high-speed serial communication systems. The proposed VCO circuit achieves wide frequency band and low gain (K_VCO) simultaneously by dividing the operating frequency range into triple-band by 2 digital control bits. A differential ring structure with a cross-coupled NMOS pair is used so that the VCO produces multiple output phases, has high operating frequency, and low phase noise. In addition, an output buffer is realized to drive heavy load at output of the VCO as well. The VCO circuit with the proposed frequency band division technique is implemented and fabricated in a 180 nm CMOS process. The post-layout simulation results illustrate that VCO circuit has good phase noise performance of -93.41 to -97.60 dBc/Hz at a 1-MHz offset and has a wide tuning range of 100 MHz to 1.65 GHz (177%). The measurement results show the output waveform of the VCO in three-band with a duty-cycle of approximately 50%. The VCO core circuit consumes 2.8 mW of power with a supply voltage of 1.8 V and occupies an area of ​​0.0546 mm².