A 2.15 GHz - 3.2 GHz DIFFERENTIAL MULTI-PASS RING OSCILLATOR ON 65 nm CMOS TECHNOLOGY

Abstract

This paper presents the design of a ring oscillator on 65 nm CMOS semiconductor technology. The oscillator consists of 8 differential delay cells, providing 16 output phases. The differential delay cell is designed without the use of a tail current source, increasing the voltage swing at the output nodes and reducing the requirement for the supply voltage. To increase the output oscillation frequency while not increasing power consumption, the ring oscillator is designed using the multi-pass architecture. In addition, in this ring oscillator, dual frequency tuning paths are used, in which coarse tuning and fine tuning are performed in digital and analog form respectively, allowing the oscillator covers a wide range of frequency from 2.15 GHz to 3.2 GHz. The proposed ring oscillator has a power consumption of 0.57 mW with a supply voltage of 0.75 V at an output frequency of 2.25 GHz, suitable for low power and low voltage applications.