FINE-GRAIN CLOCK GATING TECHNIQUE FOR A POWER SAVING 32-BIT PIPELINED MULTIPLIER IN ACTIVE MODE

Abstract

Regularly, the clock gating enable signal is generated based on coarse grain clock gating where the clock enable signal is generated from system view. This study proposes the fine grain clock gating where the clock enable signal is generated from block view. The clock enable signal is self-generated based on look ahead technique which is applied to 32-bit pipelined multiplier. A pipelined multiplier breaks multiplication process into multiple stages, where each stage performs a small part of overall multiplication. The clock gating enable signal is self-generated from each pipeline stage which can be looked ahead to gate clocks to flipflops. The proposed 32-bit look ahead clock gating (LACG) pipelined multiplier using fine-grain technique shows the ability to efficiently save power consumption compared to the normal 32-bit pipelined multiplier using coarse grain technique. The study proves results on 32-bit pipelined adder and 32-bit pipelined multiplier in terms of power consumption, utilization area and functionality. The testbench is performed by five different testcases. The simulation results show the proposed multiplier saves power consumption up to 13.2% in case of random input test case compared to the normal multiplier. However, the proposed multiplier still has more utilization area overhead than the normal pipelined multiplier.